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| PRELIMINARY Integrated Circuit Systems, Inc. LOW SKEW /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR FEATURES * 10 single ended LVCMOS outputs, 7 typical output impedance * LVPECL clock input pair * PCLK, nPCLK supports the following input levels: LVPECL, CML, SSTL * Maximum input frequency: 250MHz * Output skew: 200ps (maximum) * Part-to-part skew: 500ps (typical) * Multiple frequency skew: 350ps (maximum) * 3.3V input, outputs may be either 3.3V or 2.5V supply modes * 0C to 70C ambient operating temperature * Industrial temperature information available upon request ICS87946-01 GENERAL DESCRIPTION The ICS87946-01 is a low skew, /1, /2 Clock Generator and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS87946-01 has one LVPECL clock input pair. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 10 to 20 by utilizing the ability of the outputs to drive two series terminated lines. ,&6 The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the /1, /2 or a combination of /1 and /2 modes. The master reset input, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. The ICS87946-01 is characterized at 3.3V core/3.3V output and 3.3V core/2.5V output. Guaranteed bank, output and partto-part skew characteristics make the ICS87946-01 ideal for those clock distribution applications demanding well defined performance and repeatability. BLOCK DIAGRAM PIN ASSIGNMENT MR/nOE GND GND VDDA VDDA QA0 QA1 QA2 PCLK nPCLK DIV_SELA /1 /2 0 QA0 - QA2 1 nc 0 QB0 - QB2 1 VDD PCLK nPCLK DIV_SELA 0 QC0 - QC3 1 DIV_SELB DIV_SELC GND 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 GND QB0 VDDB QB1 GND QB2 VDDB VDDC DIV_SELB ICS87946-01 21 20 19 18 17 DIV_SELC MR/nOE 9 10 11 12 13 14 15 16 VDDC QC0 GND QC1 VDDC QC2 GND QC3 32-Lead LQFP 7mm x 7mm x 1.4mm Y Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 87946AY-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 2, 2002 1 PRELIMINARY Integrated Circuit Systems, Inc. LOW SKEW /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR Type Unused Power Input Input Input Input Input Power Power Output Pullup Description No connect. Positive supply pins. Connect to 3.3V. Pulldown Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Controls frequency division for Bank A outputs. Pulldown LVCMOS interface levels. Controls frequency division for Bank B outputs. Pulldown LVCMOS interface levels. Controls frequency division for Bank C outputs. Pulldown LVCMOS interface levels. Power supply ground. Connect to ground. Positive supply pins for Bank C outputs. Connect to 3.3V or 2.5V. ICS87946-01 TABLE 1. PIN DESCRIPTIONS Number 1 2 3 4 5 6 7 8, 11, 15, 20, 24, 27, 31 9, 13, 17 10, 12, 14, 16 18, 22 Name nc VDD PCLK nPCLK DIV_SELA DIV_SELB DIV_SELC GND VDDC QC0, QC1, QC2, QC3 VDDB QB2, QB1, QB0 VDDA QA2, QA1, QA02, Bank C outputs. LVCMOS interface levels. 7 typical output impedance. Power Positive supply pins for Bank B outputs. Connect to 3.3V or 2.5V. Bank B outputs. LVCMOS interface levels. 19, 21, 23 Output 7 typical output impedance. 25, 29 Power Positive supply pins for Bank A outputs. Connect to 3.3V or 2.5V. 26, 28, Bank A outputs. LVCMOS interface levels. Output 30 7 typical output impedance. Master reset and output enable. Resets outputs to tristate. 32 MR/nOE Input Pulldown Enables and disables all outputs. LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance VDD, *VDDx = 3.465V 51 51 TBD 7 Test Conditions Minimum Typical Maximum 4 Units pF K K pF *NOTE: VDDx denotes VDDA, VDDB, VDDC. TABLE 3. FUNCTION TABLE MR/nOE 1 0 0 0 0 0 0 87946AY-01 DIV_SELA X 0 1 X X X X Inputs DIV_SELB X X X 0 1 X X DIV_SELC X X X X X 0 1 QA0 - QA2 Hi Z fIN/1 fIN/2 Active Active Active Active Outputs QB0 - QB2 Hi Z Active Active fIN/1 fIN/2 Active Active QC0 - QC3 Hi Z Active Active Active Active fIN/1 fIN/2 REV. A JANUARY 2, 2002 www.icst.com/products/hiperclocks.html 2 PRELIMINARY Integrated Circuit Systems, Inc. LOW SKEW /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR 4.6V -0.5V to VDD + 0.5V -0.5V to VDDx + 0.5V 47.9C/W (0 lfpm) -65C to 150C ICS87946-01 ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDDx Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDX = 3.3V5%, TA = 0C TO 70C Symbol Parameter VDD Positive Supply Voltage Output Supply Voltage *VDDx Core Supply Current IDD Output Supply Current **IDDx *VDDx denotes VDDA, VDDB, VDDC. **IDDx denotes IDDA, IDDB, IDDC. Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 41 8 Maximum 3.465 3.465 Units V V mA mA TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDDX = 3.3V5%, TA = 0C TO 70C Symbol VIH VIL IIH IIL VOH VOL IOZL IOZH Parameter Input High Voltage Input Low Voltage Input DIV_SELA, DIV_SELB, High Current DIV_SELC, MR/nOE Input DIV_SELA, DIV_SELB, Low Current DIV_SELC, MR/nOE Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Tristate Current Low Output Tristate Current High Test Conditions Minimum 2 -0.3 VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -5 2.6 0.5 TBD TBD Typical Maximum VDD + 0.3 0.8 150 Units V V A A V V V V NOTE 1: Outputs terminated with 50 to VDDx/2. See page 7, Figure 1A, 3.3V Output Load Test Circuit. TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = VDDX = 3.3V5%, TA = 0C TO 70C Symbol IIH IIL VPP Parameter Input High Current Input Low Current PCLK nPCLK PCLK nPCLK Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.3 1 VDD Minimum Typical Maximum 150 5 Units A A A A V V Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 GND + 1.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V. 87946AY-01 www.icst.com/products/hiperclocks.html 3 REV. A JANUARY 2, 2002 PRELIMINARY Integrated Circuit Systems, Inc. LOW SKEW /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR Test Conditions f 250MHz f 250MHz Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 20% to 80% 20% to 80% 500 700 700 Minimum Typical Maximum 250 3.2 3.2 100 200 350 Units MHz ns ns ps ps ps ps ps ps % ns ns ICS87946-01 TABLE 5A. AC CHARACTERISTICS, VDD = VDDX = 3.3V5%, TA = 0C TO 70C Symbol fMAX tpLH tpHL Parameter Input Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Bank Skew; NOTE 2, 7 Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 tsk(b) tsk(o) tsk(w) tsk(pp) tR tF odc Output Duty Cycle 50 Output Enable Time; f = 10MHz tEN NOTE 6 Output Disable Time; f = 10MHz tDIS NOTE 6 All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. Measured at VDDx/2. NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. 87946AY-01 www.icst.com/products/hiperclocks.html 4 REV. A JANUARY 2, 2002 PRELIMINARY Integrated Circuit Systems, Inc. LOW SKEW /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 41 8 Maximum 3.465 2.625 Units V V mA mA ICS87946-01 TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDX = 2.5V5%, TA = 0C TO 70C Symbol Parameter VDD Positive Supply Voltage Output Supply Voltage *VDDx Core Supply Current IDD Output Supply Current **IDDx *VDDx denotes VDDA, VDDB, VDDC. **IDDx denotes IDDA, IDDB, IDDC. TABLE 4E. LVCMOS DC CHARACTERISTICS, VDD = 3.3V5%, VDDX = 2.5V5%, TA = 0C TO 70C Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage DIV_SELA, DIV_SELB, Input DIV_SELC, CLK_SEL, High Current nMR/OE DIV_SELA, DIV_SELB, Input DIV_SELC, CLK_SEL, Low Current nMR/OE Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Tristate Current Low Output Tristate Current High Test Conditions Minimum 2 -0.3 VDD = VIN = 3.465V Typical Maximum VDD + 0.3 0.8 150 Units V V A IIL VOH VOL IOZL IOZH VDD = 3.465V, VIN = 0V -5 1.8 0.5 TBD TBD A V V V V NOTE 1: Outputs terminated with 50 to VDDx/2. See page 7, Figure 1B, 3.3V/2.5V Output Load Test Circuit. TABLE 4F. LVPECL DC CHARACTERISTICS, VDD = VDDX = 3.3V5%, TA = 0C TO 70C Symbol IIH IIL VPP Parameter Input High Current Input Low Current PCLK nPCLK PCLK nPCLK Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.3 1 VDD Minimum Typical Maximum 150 5 Units A A A A V V Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 GND + 1.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V. 87946AY-01 www.icst.com/products/hiperclocks.html 5 REV. A JANUARY 2, 2002 PRELIMINARY Integrated Circuit Systems, Inc. LOW SKEW /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR Test Conditions f 250MHz f 250MHz Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 20% to 80% 20% to 80% 500 600 600 Minimum Typical Maximum 250 3.2 3.2 100 200 350 Units MHz ns ns ps ps ps ps ps ps % ns ns ICS87946-01 TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDX = 2.5V5%, TA = 0C TO 70C Symbol fMAX tpLH tpHL Parameter Input Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Bank Skew; NOTE 2, 7 Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 tsk(b) tsk(o) tsk(w) tsk(pp) tR tF odc Output Duty Cycle 50 Output Enable Time; f = 10MHz tEN NOTE 6 Output Disable Time; f = 10MHz tDIS NOTE 6 All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. Measured at VDDx/2. NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. 87946AY-01 www.icst.com/products/hiperclocks.html 6 REV. A JANUARY 2, 2002 PRELIMINARY Integrated Circuit Systems, Inc. LOW SKEW /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR ICS87946-01 PARAMETER MEASUREMENT INFORMATION 1.65V5% V DD VDDx SCOPE LVCMOS GND Qx -1.65V5% FIGURE 1A - 3.3V OUTPUT LOAD TEST CIRCUIT 2.05V5% 1.25V5% VDD VDDx SCOPE LVCMOS GND Qx -1.25V5% FIGURE 1B - 3.3V/2.5V OUTPUT LOAD TEST CIRCUIT 87946AY-01 www.icst.com/products/hiperclocks.html 7 REV. A JANUARY 2, 2002 PRELIMINARY Integrated Circuit Systems, Inc. LOW SKEW /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR VDD ICS87946-01 nPCLK V PCLK PP Cross Points V CMR GND FIGURE 2 - DIFFERENTIAL INPUT LEVEL Qx Vx DD 2 V Qy DD x 2 tsk(o) FIGURE 3 - OUTPUT SKEW PART 1 Qx V DD x 2 PART 2 Qy V DD x 2 tsk(pp) FIGURE 4 - PART-TO-PART SKEW 87946AY-01 www.icst.com/products/hiperclocks.html 8 REV. A JANUARY 2, 2002 PRELIMINARY Integrated Circuit Systems, Inc. LOW SKEW /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR 80% 80% V 20% 20% t t SWING ICS87946-01 Clock Inputs and Outputs R F FIGURE 5 - INPUT AND OUTPUT RISE AND FALL TIME nPCLK PCLK V DDx QAx, QBx, QCx 2 t PD FIGURE 6 - PROPAGATION DELAY Vx DD 2 QAx, QBx, QCx Pulse Width t t odc = t PW PERIOD PERIOD FIGURE 7 - odc & tPERIOD 87946AY-01 www.icst.com/products/hiperclocks.html 9 REV. A JANUARY 2, 2002 PRELIMINARY Integrated Circuit Systems, Inc. LOW SKEW /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION ICS87946-01 WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K CLK_IN + V_REF C1 0.1uF R2 1K FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 87946AY-01 www.icst.com/products/hiperclocks.html 10 REV. A JANUARY 2, 2002 PRELIMINARY Integrated Circuit Systems, Inc. LOW SKEW /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION ICS87946-01 TABLE 6. JAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W 200 55.9C/W 42.1C/W 500 50.1C/W 39.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS87946-01 is: 1204 87946AY-01 www.icst.com/products/hiperclocks.html 11 REV. A JANUARY 2, 2002 PRELIMINARY Integrated Circuit Systems, Inc. LOW SKEW /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR ICS87946-01 PACKAGE OUTLINE - Y SUFFIX TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM Reference Document: JEDEC Publication 95, MS-026 87946AY-01 www.icst.com/products/hiperclocks.html 12 REV. A JANUARY 2, 2002 PRELIMINARY Integrated Circuit Systems, Inc. LOW SKEW /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR Marking ICS87946AY-01 ICS87946AY-01 Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature 0C to 70C 0C to 70C ICS87946-01 TABLE 8. ORDERING INFORMATION Part/Order Number ICS87946AY-01 ICS87946AY-01T While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87946AY-01 www.icst.com/products/hiperclocks.html 13 REV. A JANUARY 2, 2002 |
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